Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Table 2.3: PIC18F452 configuration register descriptions
| Configuration bits | Description |
|---|---|
| OSCSEN | Clock source switching enable |
| FOSC2:FOSC0 | Oscillator modes |
| BORV1:BORV0 | Brown-out reset voltage |
| BOREN | Brown-out reset enable |
| PWRTEN | Power-up timer enable |
| WDTPS2:WDTPS0 | Watchdog timer postscale bits |
| WDTEN | Watchdog timer enable |
| CCP2MX | CCP2 multiplex |
| DEBUG | Debug enable |
| LVP | Low-voltage program enable |
| STVREN | Stack full/underflow reset enable |
| CP3:CP0 | Code protection |
| CPD | EEPROM code protection |
| CPB | Boot block code protection |
| WRT3:WRT0 | Program memory write protection |
| WRTD | EPROM write protection |
| WRTB | Boot block write protection |
| WRTC | Configuration register write protection |
| EBTR3:EBTR0 | Table read protection |
| EBTRB | Boot block table read protection |
| DEV2:DEV0 | Device ID bits (001 = 18F452) |
| REV4:REV0 | Revision ID bits |
| DEV10:DEV3 | Device ID bits |