The architecture of PORTA is shown in Figure 2.22. There are three registers associated with PORTA:
• Port data register — PORTA
• Port direction register — TRISA
• Port latch register — LATA
Figure 2.22: PIC18F452 PORTA RA0–RA3 and RA5 pins
PORTA is the name of the port data register. The TRISA register defines the direction of PORTA pins, where a logic 1 in a bit position defines the pin as an input pin, and a 0 in a bit position defines it as an output pin. LATA is the output latch register which shares the same data latch as PORTA. Writing to one is equivalent to writing to the other. But reading from LATA activates the buffer at the top of the diagram, and the value held in the PORTA/LATA data latch is transferred to the data bus independent of the state of the actual output pin of the microcontroller.
Bits 0 through 3 and 5 of PORTA are also used as analog inputs. After a device reset, these pins are programmed as analog inputs and RA4 and RA6 are configured as digital inputs. To program the analog inputs as digital I/O, the ADCON1 register (A/D register) must be programmed accordingly. Writing 7 to ADCON1 configures all PORTA pins as digital I/O.
The RA4 pin is multiplexed with the Timer 0 clock input (T0CKI). This is a Schmitt trigger input and an open drain output.
RA6 can be used as a general purpose I/O pin, as the OSC2 clock input, or as a clock output providing FOSC/4 clock pulses.
In PIC18F452 microcontroller PORTB is an 8-bit bidirectional port shared with interrupt pins and serial device programming pins. Table 2.7 gives the PORTB bit functions.
Table 2.7: PIC18F452 PORTB pin functions
| Pin | Description |
|---|---|
| RB0/INT0 | |
| RB0 | Digital I/O |
| INT0 | External interrupt 0 |
| RB1/INT1 | |
| RB1 | Digital I/O |
| INT1 | External interrupt 1 |
| RB2/INT2 | |
| RB2 | Digital I/O |
| INT2 | External interrupt 2 |
| RB3/CCP2 | |
| RB3 | Digital I/O |
| CCP2 | Capture 2 input, compare 2, and PWM2 output |
| RB4 | Digital I/O, interrupt on change pin |
| RB5/PGM | |
| RB5 | Digital I/O, interrupt on change pin |
| PGM | Low-voltage ICSP programming pin |
| RB6/PGC | |
| RB6 | Digital I/O, interrupt on change pin |
| PGC | In-circuit debugger and ICSP programming pin |
| RB7/PGD | |
| RB7 | Digital I/O, interrupt on change pin |
| PGD | In-circuit debugger and ICSP programming pin |
PORTB is controlled by three registers:
• Port data register — PORTB
• Port direction register — TRISB
• Port latch register — LATB
The general operation of PORTB is similar to that of PORTA. Figure 2.23 shows the architecture of PORTB. Each port pin has a weak internal pull-up which can be enabled by clearing bit RBPU of register INTCON2. These pull-ups are disabled on a power-on reset and when the port pin is configured as an output. On a power-on reset, PORTB pins are configured as digital inputs. Internal pull-ups allow input devices such as switches to be connected to PORTB pins without the use of external pull-up resistors. This saves costs because the component count and wiring requirements are reduced.