Read/write signals tell the RAM and the I/O chip whether they have to read, i.e. accept information from the data bus or to write information onto the data bus.
Chip select is the on/off switch for each of the chips and we have to be very careful to ensure that only one set of information is being connected to the data bus at one time.
If a ROM chip were to be putting a binary 0 onto one of the data bus connections and, at the same time, another ROM or a RAM chip was applying a binary 1, there would be a disagreement between the two chips. What would happen? It is sad but the likely outcome is a fight to the finish with one or other of the chips being condemned to the waste bin.
To prevent this from happening, an address decoder circuit samples the address bus and selects the appropriate chip. If the microprocessor wishes to send some data to the RAM chip, it applies a suitable address to the address bus that is applied to the ROM, RAM and the I/O controller but there are no problems at the moment since all these chips are switched off. The address decoder applies the inputs from the address bus to an array of logic gates that have been organized to comply with the memory map of the system. The output from the address decoder then switches the RAM chip on and the ROM and I/O chips off. The design of the address decoder can be modified to control any number of external chips in the system. An upgraded system is shown in Figure 7.6.
Figure 7.6 A complete microprocessor system
To demonstrate its operation we can ask it to perform a simple task. Instruction: Send the number 25H which is in the ROM and store it in the RAM at address 2500H. This is what happens – follow the action on Figure 7.6.
1 The microprocessor has to collect the instruction from an address in ROM. It does this by putting the address onto the address bus.
2 The address is applied to the ROM and the RAM as well as the address decoder. This will not cause any problems because all the chip selects will be switched off at the moment. When the logic gates within the address decoder responds to the input from the address bus the result will be that the ROM is switched on and the other two are kept off.
3 Switching on the ROM will mean that it takes in the address from the address bus. Inside the ROM chip, the row and column decoders activate one of the memory locations and the binary number stored at that location is placed on the data bus by switching on the tri-state buffers. As soon as the information is read, the chip select will switch the ROM chip off.
4 The information which is now on the data bus is read by the microprocessor. It is an instruction which can be interpreted as ‘go to address F600H and read the number that is stored in that address’.
5 In response to this instruction, the microprocessor puts the address F600H onto the address bus.
6 The address decoder applies this number to its logic gates and this results in the chip select of the ROM chip being switched on again. The ROM chip accepts the address F600H into its row and column decoders and then puts the number 25H onto the data bus.
7 This number is stored temporarily in the microprocessor.
8 The microprocessor then puts the number 2500H onto the address bus and the address decoder puts a signal on the chip select of the RAM chip to switch it on. It then sends a logic 1 on the read/write line. The RAM is switched on and it is told to read the data on the data bus. The read/write line goes to the I/O chip as well but again, this causes no problem because its chip select line is keeping it switched off.
The number 25 is now safely stored in the RAM chip and will remain there until it is over-written with new information or the power is switched off.
We have seen in Chapter 6 that the number of locations that can be addressed is 2n where n is the number of address lines. By feeding the numbers into our calculators we can see that the relationship between lines and locations is as shown in Table 7.1.
Table 7.1 Larger memories need more address lines
| Number of address lines | Number of locations | Number of address lines | Number of locations | Number of address lines | Number of locations |
|---|---|---|---|---|---|
| 1 | 2 | 13 | 8k | 25 | 32M |
| 2 | 4 | 14 | 16k | 26 | 64M |
| 3 | 8 | 15 | 32k | 27 | 128M |
| 4 | 16 | 16 | 64k | 28 | 256M |
| 5 | 32 | 17 | 128k | 29 | 512M |
| 6 | 64 | 18 | 256k | 30 | 1024M=1G |
| 7 | 128 | 19 | 512k | 31 | 2G |
| 8 | 256 | 20 | 1024k=1M | 32 | 4G |
| 9 | 512 | 21 | 2M | 33 | 8G |
| 10 | 1024 = 1k | 22 | 4M | 34 | 16G |
| 11 | 2k | 23 | 8M | 35 | 32G |
| 12 | 4k | 24 | 16M | 36 | 64G |
We can also use this table to identify the number of lines needed to access a known number of address locations. For example, if we wanted to access 700 locations, we can see that 9 lines could access 512 locations which is too few. Therefore, we would have to go to 10 lines which would actually give access to 1024 locations. The ‘real’ answer of 9.45 is not sensible because we cannot have 0.45 of a connecting wire so if 9 is not enough, it will have to be 10. For those who like to see the calculations, the mathematical result is given by:
Designing a decoding circuit
Let’s imagine that we have a microprocessor-based system using eight memory chips, ROM or RAM it doesn’t matter. Each of the chips holds 8 kbytes of memory. From Table 7.1 we can see that an 8 kbytes chip will require 13 address lines in order to access each of their internal locations. Assume too, that the microprocessor that we are using has a 16-bit address bus so we have the situation shown in Figure 7.7. The address lines are numbered from A0 (address line number 0) to A15. The 13 bits A0–A12 are heading off towards the ROM and RAM chips. The remaining three address lines, A13–A15, are used by the address decoder.
Figure 7.7 There are three ‘spare’ address lines
The decoding chip
The decoder circuit can be made from separate logic gates or can be bought ready-built in a single integrated circuit. For ease of construction, most designers opt for this choice for the result is smaller, dissipates less heat and is less expensive (and it works first time). There is very little to be said for the build-it-yourself approach.