A logic analyser may miss it because the incoming data is sampled once per pulse and if it misses the glitch it will not be recorded. To overcome this, the logic analyser can use its own internal clock that is running much faster than the system clock so a single logic one may extend for 10 or 20 bits in the register and a glitch may well be recorded. Figure 18.9 shows the internal clock running at 10 times the microprocessor clock. Some logic analysers have a built-in glitch catcher and use it to capture the correct section of data. As we can see, the logic analyser is a very useful and sophisticated piece of kit. Using it, however, is a slow process. There are lots of connections to be made to the circuit and much sitting and thinking.
Figure 18.9 Glitch catching
In each case, choose the best option.
1 Damage due to static electricity:
(a) can only occur in the winter.
(b) is best prevented by wearing wet clothing.
(c) is only possible in carpeted areas.
(d) can be reduced by wearing a grounded wrist strap.
2 If the two power supplies were connected as in Figure 18.10, the result would be:
(a) smoke pouring from both power supplies.
(b) an output of +5 V but twice as much current.
(c) an output of +10 V.
(d) no output but no smoke either.
Figure 18.10
3 The arrow in Figure 18.11 indicates pin:
(a) 2.
(b) 8.
(c) 11.
(d) 16.
Figure 18.11
4 A logic probe:
(a) indicates whether your fault-finding technique is based on sound reasoning.
(b) can detect the difference between a disconnection and a grounded connection.
(c) can store a stream of data.
(d) detects the presence of static electricity.
5 A logic analyser quoted as 20 channels × 1024 bits:
(a) will show a four digit hex number in its window.
(b) can monitor any 1024 points at the same time.
(c) would store a total of 1044 bits of data.
(d) can monitor any 20 points at the same time.
Appendix A: Special function register file
| Addr | Name | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Power-on Reset | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| BANK 0 | ||||||||||||
| 00H | Uses contents of FSR to address data memory (not a physical register) | |||||||||||
| 01H | TMRO | 8-bit real-time clock/counter | xxxxxxxx | |||||||||
| 02H | PCL | Low order 8 bits of the program counter (PC) | 00000000 | |||||||||
| 03H | Status | IRP | RP1 | RPO | TO | PD | Z | DC | C | 00011xxx | ||
| 04H | FSR | Indirect Data Mamory Address Pointer | xxxxxxxx | |||||||||
| 05H | PortA | – | – | – | RA4/T-CKI | RA3 | RA2 | RA1 | RA0 | ---x xxxx | ||
| 06H | PortB | RB7 | RB6 | RB5 | RB4 | RB3 | RB2 | RB1 | RB0/INT | xxxxxxxx | ||
| 07H | – | Unused | ||||||||||
| BANK 1 | ||||||||||||
| 81H | Option | RBPU | INTEDG | T0CS | T0SE | PSA | PS2 | PS1 | PS0 | 11111111 | ||
| 85H | TRISA | – | – | – | PortA data Direction | ---11111 | ||||||
| 86H | TRISB | PortB data Direction | 11111111 | |||||||||
| 87H | – | Unused | ||||||||||
| 88H | EECON 1 | – | – | – | EEIF | WRERR | WREN | WR | RD | ---0x000 | ||
| 89H | EECON 2 | EEPROM control reg. (not a physical register) | ------- | |||||||||
The full details (85 pages) of absolutely everything about the PIC16F84A (or any other PIC) can be downloaded from www.microchip.com.
Appendix B: PIC 16CXXX instruction set
| Syntax | Description | Status affected |
|---|---|---|
| ADDLW k | The contents of the W register are added to an 8-bit number and the result put in the W reg. | C, DC, Z |
| ADDWF f,d | Add the contents of the W and f registers. If d=0 the result goes to W. If d=1 the result goes to the f register | C, DC, Z |
| ANDLW k | The contents of the W register are ANDed with an 8-bit number and the result put in the W reg. | Z |
| ANDWF f,d | AND w with reg f. If d=0 the result goes to W. If d=1 the result goes to the f register | Z |
| BCF f,b | Bit b in reg f is cleared | |
| BSF f,b | Bit b in reg f is set | |
| BTFSS f,b | If bit b in reg f=0, the next instruction in executed. If it is 1 the next instr. is replaced with a NOP | 1 or 2 cycles |
| BTFSC f,b | If bit b in reg f=1, the next instruction in executed. If it is 0 the next instr. is replaced with a NOP | 1 or 2 cycles |
| CALL k | Call subroutine. Return address (PC+1) is pushed onto stack. The 11-bit immediate address is loaded into PC bits 1:0 The upper bits of the PC are loaded from PCLATH 4:3. | 2 cycle |
| CLRF | f Register f is cleared and Z flag is set. | Z |
| CLRW | Register W is cleared and Z flag is set. | Z |
| CLRWDT | Resets watchdog timer and watchdog prescaler | TO, PD |
| COMF f,d | Contents of ‘f’ are complemented (0→1, 1→0) If d=0 the result goes to W. If d=1 the result goes to f | Z |
| DECF f,d | Contents of ‘f’ reduced by 1. If d=0 the result goes to W. If d = 1 the result goes to f | Z |
| DECFSZ f,d | Contents of ‘f’ reduced by 1. if d=0 the result goes to W. If d=1 the result goes to f. If result = 1, the next instruction in executed. If it is 0 the next instr. is replaced with a NOP | 1 or 2 cycles |
| GOTO k | The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH <4:3>. | |
| INCF f,d | If d=0 the result goes to W. If d=1, result goes to f. | |
| INCFSZ f,d | Contents of ‘f’ incremented. If d=0 the result goes to W. If d=1 the result goes to f. If rfesult = 1, the next instruction is executed. If it is 0 the next instr. is replaced with a NOP | 1 or 2 cycles |
| IORLW k | The contents of the W register are ANDed with an 8-bit number and the result put in the W reg. | Z |
| IORFWF f,d | The contents of the W register are Inclusive ORed with reg. F. If d=1 resujlt goes back into f | |
| MOVF f,d | If d=0, contents of f goes to W reg. If d=1 it goes to f | Z |
| MOVLW k | The 8-bit number k goes into W. | |
| MOVWF f | Moves data from W register to f register | |
| NOP | Does nothing – just a time waster (one cycle period) | |
| RETFIE | Return from interrupt. Top of stack→PC, 1→GIE | 2 cycle |
| RETLW k | W reg loaded with number , return address→PC | 2 cycle |
| RETURN | Return from subroutine. Return address→PC | 2 cycle |
| RLF f,d | Contents of ‘f’ are rotated left one bit via the carry flag. If d=0 the result goes to W. Id=1, result goes back to f. See fig. below | C |
| SLEEP | Powerdown status bit PD is cleared, Timeout status bit TO is set. WDT and prescaler are cleared, oscillator stops and controller goes to sleep. | TO, PD |
| SUBLW k | W register subtracted from the number k, result goes into W reg. (2’s complement method) | C, DC, Z |
| SUBWF f,d | W register subtracted from the register f. If d=0 the result goes to W. If d=1 the result goes to f. (2’s complement method) | C, DC, Z |
| SWAPF f,d | Upper and lower nibbles of f are exchanged. If d=0 the result goes to W. If d=1 the result goes to f. | |
| XORLW k | W register contents XOR’ed with the number k, result goes into W reg. | Z |
| XORWF f,d | W register contents XOR’ed with the register f, if d=0 the result goes to W. If d=1 the result goes to f | Z |